There is conventionally known data processors that perform access operations involving a wait state on accessible devices running at low speed. This type of data processor causes the CPU to wait temporarily upon access to a low-speed accessible device by feeding a chip select signal back to a wait terminal of the CPU.
FIG. 1 is a view showing a constitution of such a conventional data processor. In FIG. 1, reference numeral 1 stands for a CPU providing overall control of the data processor; 2 for an address decoder for decoding addresses output by the CPU 1; 3 for an I/O device at a low-speed (called the low-speed device hereunder) among configured I/O devices as accessible devices assigning a predetermined address; and 4 for an address/data bus linking the CPU 1, the address decoder 2 and the low-speed device 3. Reference numeral 5 for a chip select signal output from the address decoder 2; 6 for a read signal output from the CPU 1; and 7 for a write signal also output by the same. Reference numeral 8 for a chip select terminal of the low-speed device 3; and 9 for a wait terminal of the CPU 1.
Next, operations will be described.
When the CPU 1 is to read data from the low-speed device 3, the CPU 1 first places onto the address/data bus 4 a target intra-device address from which to read the data. The address from the CPU 1 is sent to the address decoder 2, and the address decoder 2 decodes the received address and outputs accordingly a chip select signal 5 to select the predetermined accessible device. This chip select signal 5 is input to the chip select terminal 8, whereby the low-speed device 3 is selected.
The low-speed device 3 selected by the chip select signal 5 outputs data onto the address/data bus 4 when the read signal 6 is received from the CPU 1. At this point, however, since the chip select signal 5 is being fed back to the wait terminal 9 of the CPU 1, the CPU 1 performs a wait operation. After this wait operation, the data placed by the low-speed device 3 onto the address/data bus 4 are read into the CPU 1 in accordance with the read signal 6.
Then, when the CPU 1 is to write data to the low-speed device 3, the CPU 1 first outputs onto the address/data bus 4 a target intra-device address to which to write the data, as in the case of reading data. The address decoder 2 decodes the received address and outputs accordingly a chip select signal 5, and the chip select signal 5 is input to the chip select terminal 8 of the low-speed device 3, whereby the device 3 is selected.
After placing the address onto the address/data bus 4, the CPU 1 outputs a write signal 7 causing the data to be output onto the bus 4. At this point, however, since the chip select signal 5 is being fed back to the wait terminal 9 of the CPU 1, the CPU 1 performs the wait operation. After this wait operation, the data placed onto the address/data bus 4 are written to the low-speed device 3 in accordance with the write signal 7 from the CPU 1.
Since the conventional data processor has the above constitution, the addresses to be accessed through wait operations are fixed by the address decoder 2. To change such addresses requires performing troublesome circuit modifications involving the replacement of the address decoder 2, thus there is a problem.
In addition, there is a problem that when the wait access depends on the address, so that if the low-speed device 3 having different read and write access speeds, i.e., a high-speed for read access and a low-speed for write access, is used, the CPU 1 must wait for a redundant time if it is met to the write access speed, and on the other hand, the data cannot be written if it is met to the read access speed.
Furthermore, in recent years, although system control programs are written in a flash memory in microcomputer-applied systems, some of these systems may have their programs written to an expensive flash memory at their prototype trial stage and later to an inexpensive one-time ROM (read-only memory) at the commercial stage. In such cases, for the above-described reasons, there is a problem that the read access speed may become lower than desired (i.e., the operating speed of the entire system is reduced unacceptably), or it may become impossible to write data to the flash memory.
Techniques related to the above-described type of conventional data processor are disclosed illustratively in JP-A No. Sho 62-217350, as well as in JP-A No. Hei 3-99354.
The apparatus discussed in the above-cited JP-A No. Sho 62-217350 involves a CPU equipped with storage means for storing, in a concentrated manner, a response speed corresponding to each of the I/O devices configured. Every time any one of the I/O devices is selected, the corresponding information held in the storage means is read out as the reference speed for performing a wait operation. In that case, since the wait operation is carried out at the time of the selection of an I/O device, there is a problem that it is impossible for any program to freely set or cancel wait operations independently of the address space or read/write access.
In addition, the apparatus described in the above-cited JP-A No. Hei 3-99354 performs wait operations when, upon receipt of a ready signal from a memory or an I/O device, the active position of the ready signal to be transmitted to the CPU is changed in a programmable manner. In this case, the fact that signals are received from the memory and I/O devices demands inevitable dependence for control on the address space, thus there is a problem.
The present invention is achieved to overcome the above-described drawbacks and disadvantages and to obtain a data processor which eliminates the need for troublesome circuit modifications when a wait operation becomes necessary for each read or write access because the address space of the CPU is altered or because a memory or any of configured I/O devices is changed, the data processor allowing a suitable program to set or cancel wait operations as desired and free of constraints dictated conventionally by the address space or read/write access.